A current trend in the fabrication of CMOS devices is to use various techniques, known in the industry as “shrinks,” to reduce the size of the device and thus enable fabrication of a greater number of devices per each semiconductor wafer or other substrate. The rapid numbers of shrinks a given device may go through presents several challenges. Some of those challenges involve isolation between intra-well and inter-well isolation regions. Intra-well isolation is defined as the isolation between similarly doped field effect transistors. For example, n-channel field effect transistors (FETs) that reside within a common p-well region must be isolated from each other so that there is minimal interaction between the neighboring FETs. Likewise, isolation is needed between p-channel FETs that reside in a common n-well region.
Inter-well isolation is defined as the isolation between similar type dopants of a FET and a neighboring conductively doped region. For example, n-channel FETs that reside close to a neighboring n-well region require sufficient isolation to minimize the leakage current between the n-channel devices and the neighboring n-well region, that will result in isolation breakdown. Likewise, isolation is required for p-channel FETs that reside close to a neighboring p-well region.
Due to rapidly shrinking die sizes of devices, the spacing allowed for intra-well and inter-well isolation is becoming increasingly tight. The present invention provides sufficient inter-well and intra-well isolation for CMOS devices.